DEFINITIONS
The following definitions will be helpful to the reader for understanding the description:
ALU:
An ALU (Arithmetic and Logic Unit) is a logic mechanism capable of computing arithmetic (addition, subtraction, etc . . . ) and logic operations (and, or, etc . . . ).
Operation:
An operation is the tiniest executable command a processor is capable of handling. (example: ALU operation, Memory operation, etc . . . ).
Instruction:
An instruction is the content of one word of the Instruction Store. It may be composed of one or multiple operations. For example a VLIW (Very Long Instruction Word) instruction specifies more than one concurrent operations.
ALU Operation:
An ALU operation is an operation involving an Arithmetic and Logic Unit. ALU operations are arithmetic (addition, subtraction, . . . ) or logic (and, or, . . . ) operations.
IO Operation:
An IO (input/Output) operation is an operation capable of accessing an external device using read and write operations (example: load I0, store I0, etc . . . )
Memory Operation:
A memory operation is an operation capable of accessing an external memory using read and write operations (example: load local memory, store local memory, etc . . . )
Branch:
An instruction may point to the next instruction address (for example 103 to 104), or to any other instruction address (for. example 103 to 221). The fact of going to an instruction address different from the next one is called a branch.
Basic Block:
A basic block is a set of instructions placed between two consecutive branch operations.
Branch Operation:
A branch operation is an operation capable or routing the program to a new address distinct from the next address (present address plus one).
Multiport Array:
A multiport array is a set of registers where multiple registers can be written or read at the same time.
Ports:
Each set of wires necessary to perform a read or write operation is called a port. For example, a multiport array can have two write ports, and four read ports. Two distinct data in two distinct addresses can be written and four distinct data from four distinct addresses can be read at the same time.
Processor Cycle:
A processor is composed of a set of logic elements, all timed (allowed to change value) at discrete instants. These instants are periodical, and the period is called processor cycle.
Source Registers:
The input data of an instruction are in registers called source registers.
Target Register:
The result of an instruction is assigned to a register called target register.
Shadow register:
As it is not known whether speculative operations must take place or not, results of these operations are assigned to registers different from target registers. These registers are called shadow registers.